NDLI: Emerging Techniques for Test Data Compression

Content Provider	IEEE Xplore Digital Library
Author	Balakrishnan, K.J.
Copyright Year	2005
Description	Author affiliation: NEC Labs. America, Princeton, NJ (Balakrishnan, K.J.)
Abstract	Increasing test costs has been one of the disadvantageous consequences of technology scaling especially in deep sub-micron designs. The amount of test data required to achieve good test quality has increased tremendously due to the increasing complexity of devices as well as the need to test for newer defect mechanisms that are becoming predominant in smaller device geometries. This has led to the development and deployment of new design-for-test (DFT) technologies to mitigate the problem. Test data compression has been at the forefront of solutions to reduce test costs through reduction in tester storage and test application time. In addition, it has the advantage of needing minimal changes to traditional design flow. The popularity and wide adoption of test data compression can be gauged by the fact that almost all EDA vendors now include test compression with their test solutions. Most test data compression techniques have concentrated on scan test vectors since the bulk of the increase in test data is due to scan vectors, including both stuck-at and delay tests. The test data of scan vectors consist of two parts - the test input or stimulus which is loaded into the scan chains and the test response which is captured at the scan cells after the capture cycle and unloaded through the scan chains for comparison with the correct response. The compression of both these parts present different challenges and hence require separate schemes. The input compression should be loss-less (to avoid reduction in fault coverage) while the response compression is complicated by the presence of unknown values (X's) that are captured in the scan cells. This presentation first briefly summarizes current test data compression techniques. Most of the commercial tools for test data compression utilize on-chip circuits for decompression that belong to the category of linear decompressors. We discuss the limitations of current schemes and look at future challenges. Subsequently, we talk about emerging techniques that seek to overcome these challenges. Several techniques have been developed at NEC Labs for both input test data compression and output (response) compaction. XWRC (Wang et al., 2005) is an externally loaded weighted random pattern compression scheme that combines weighted random pattern testing and LFSR reseeding to achieve very high input compression. PIDISC (Balakrishnan et al., 2006) is a pattern and design independent seed compression scheme to further compress the seeds of LFSR in reseeding based compression schemes. On the output side, a novel compactor to handle test responses with unknown values has been developed (Chao et al., 2005). Response Shaper (2005) is a technique to eliminate the reduction in fault coverage in spatial response compaction due to error masking caused by the appearance of unknown values and even errors. XBlock (Wang et al., 2006) is an efficient LFSR reseeding based technique to block unknown values for temporal compactors
Starting Page	462
Ending Page	462
File Size	92797
Page Count	1
File Format	PDF
ISBN	0769524818
ISSN	10817735
DOI	10.1109/ATS.2005.57
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-18
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Test data compression Testing Costs Design for testability Circuit faults Compaction Geometry Electronic design automation and methodology Delay National electric code
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Test data compression and compaction for embedded test of nanometer technology designs

Design for primitive delay fault testability

On combining design for testability techniques

Design for testability to combat delay faults

Proactive management of X's in scan chains for compression

A low overhead design for testability and test generation technique for core-based systems

A low cost test data compression technique for high n-detection fault coverage

High-level test compaction techniques

An application of partial scan techniques to a high-end system LSI design

Emerging Techniques for Test Data Compression

Similar Documents

Test data compression and compaction for embedded test of nanometer technology designs

Design for primitive delay fault testability

On combining design for testability techniques

Design for testability to combat delay faults

Proactive management of X's in scan chains for compression

A low overhead design for testability and test generation technique for core-based systems

A low cost test data compression technique for high n-detection fault coverage

High-level test compaction techniques

An application of partial scan techniques to a high-end system LSI design

Emerging Techniques for Test Data Compression