NDLI: Peak-power reduction for multiple-scan circuits during test application

Content Provider	IEEE Xplore Digital Library
Author	Kuen-Jong Lee Tsung-Chu Haung Jih-Jeen Chen
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan (Kuen-Jong Lee)
Abstract	This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.
Starting Page	453
Ending Page	458
File Size	616476
Page Count	6
File Format	PDF
ISBN	0769508871
ISSN	10817735
DOI	10.1109/ATS.2000.893666
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-12-06
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Power dissipation Broadcasting Energy consumption Land surface temperature Interleaved codes Added delay System-on-a-chip System testing Data engineering
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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