NDLI: Synthesizing for scan dependence in built-in self-testable designs

Content Provider	IEEE Xplore Digital Library
Author	Avra, L.J. McCluskey, E.J.
Copyright Year	1993
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA (Avra, L.J.; McCluskey, E.J.)
Abstract	This paper introduces new design and synthesis techniques that reduce the area and performance overhead of built-in self-test (BIST) architectures such as circular BIST and parallel BIST. Our goal is to arrange the system bistables into scan paths such that some of the BIST and scan logic is shared with the functional logic. Logic sharing is possible when scan dependence is introduced in the design. Other BIST design techniques attempt to avoid scan dependence because it can reduce the fault coverage of embedded, multiple input signature registers (MISRs). We show that introducing certain types of scan dependence in embedded MISRs can result in reduced overhead and improved fault coverage. We present our results for benchmark circuits that have been synthesized to take advantage of scan dependence in a circular BIST architecture.
Starting Page	734
Ending Page	743
File Size	1038786
Page Count	10
File Format	PDF
ISBN	0780314301
DOI	10.1109/TEST.1993.470629
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-17
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Hardware Reconfigurable logic Logic design Circuit synthesis Automatic testing Life testing Costs Logic testing
Content Type	Text
Resource Type	Article

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