NDLI: Accelerating functional simulation for processor based designs

Content Provider	IEEE Xplore Digital Library
Author	Klein, R. Piekarz, T.
Copyright Year	2005
Description	Author affiliation: Mentor Graphics Corp., Wilsonville, OR, USA (Klein, R.; Piekarz, T.)
Abstract	Design verification is taking an increasing proportion of the design cycle of system-on-chip (SoC) designs. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems based in 2004 IC/ASIC Functional Verification Study (2005). Running regression suites against the design can take up to several years of CPU time to complete. In this paper we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system level verification. As shown in various hardware/software co-verification tools as stated in R. Klein (1996) and M. Stanbro (1998), the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor's memory space between the logic simulation and the processor model.
Sponsorship	iCore Western Econ. Diversification Canada Alberta Innovation & Sci. Ind. Canada CMC Microsystems
Starting Page	323
Ending Page	328
File Size	137461
Page Count	6
File Format	PDF
ISBN	0769524036
DOI	10.1109/IWSOC.2005.34
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-20
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Process design Hardware Software testing System-on-a-chip Integrated circuit testing System testing Application specific integrated circuits Software tools Design engineering
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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