NDLI: HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Joven, J. Strict, P. Castells-Rufas, D. Bagdia, A. De Micheli, G. Carrabina, J.
Copyright Year	2011
Description	Author affiliation: LSI-EPFL, Station 14, 1015 Lausanne, Switzerland (Joven, J.; De Micheli, G.) \|\| CEPHIS-MISE, Campus UAB, Building Q (ETSE), 08193 Bellaterra, Spain (Castells-Rufas, D.; Carrabina, J.) \|\| ARM Ltd, 110 Fulbourn Rd, Cambridge CB1 9NJ, United Kingdom (Strict, P.; Bagdia, A.)
Abstract	Nowadays industrial monoprocessor and multiprocessor systems make use of hardware floating-point units (FPUs) to provide software acceleration and better precision due to the necessity to compute complex software applications. This paper presents the design of an IEEE-754 compliant FPU, targeted to be used with ARM Cortex-M1 processor on FPGA SoCs. We face the design of an AMBA-based decoupled FPU in order to avoid changing of the Cortex-M1 ARMv6-M architecture and the ARM compiler, but as well to eventually share it among different processors in our Cortex-M1 MPSoC design. Our HW-SW implementation can be easily integrated to enable hardware-assisted floating-point operations transparently from the software application. This work reports synthesis results of our Cortex-M1 SoC architecture, as well as our FPU in Altera and Xilinx FPGAs, which exhibit competitive numbers compared to the equivalent Xilinx FPU IP core. Additionally, single and double precision tests have been performed under different scenarios showing best case speedups between 8.8× and 53.2× depending on the FP operation when are compared to FP software emulation libraries.
Starting Page	1
Ending Page	8
File Size	3604438
Page Count	8
File Format	PDF
ISBN	9781612848181
e-ISBN	9781612848204
e-ISBN	9781612848198
DOI	10.1109/SIES.2011.5953649
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-15
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Registers Computer architecture Hardware Protocols Software Fabrics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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