NDLI: BTI impact on logical gates in nano-scale CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Khan, S. Hamdioui, S. Kukner, H. Raghavan, P. Catthoor, F.
Copyright Year	2012
Description	Author affiliation: Computer Engineering Laboratory, Delft University of Technology, Mekelweg 4, 2628 CD, The Netherland (Khan, S.; Hamdioui, S.) \|\| Kapeldreef 75,B-3001, Leuven, Belgium (Kukner, H.; Raghavan, P.; Catthoor, F.)
Abstract	As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistors- has become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND and NOR) and complex gates while considering the impact of input's duty cycle, the frequency at which they change, as well as the impact of the stressed transistor location. The simulation results show that the impact of BTI is strongly gate dependent and that in general the impact in complex gates is larger. When considering both NBTI and PBTI for basic gates, the results reveal that for a NOR gate the impact of NBTI is 2.19× higher than that of PBTI; while for a NAND gate, PBTI impact is 1.27× higher than that of NBTI. When considering different input duty cycles and their frequencies, the results show that the higher the duty cycle, the lower NBTI impact and the higher the PBTI impact regardless of the gate types and the frequency; a variation of ±30% duty cycle causes a variation of up to 49% variation in the impact of NBTI and a variation of 16% in the impact of PBTI. For complex gates, the results show similar trends, but with higher impact.
Starting Page	348
Ending Page	353
File Size	934022
Page Count	6
File Format	PDF
ISBN	9781467311878
e-ISBN	9781467311885
e-ISBN	9781467311861
DOI	10.1109/DDECS.2012.6219086
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-18
Publisher Place	Estonia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Delay MOSFETs Stress Degradation Organizations stress location NBTI PBTI Complex gates duty cycle frequency
Content Type	Text
Resource Type	Article

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