NDLI: Incremental SAT Instance Generation for SAT-based ATPG

Please wait, while we are loading the content...

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems

Table of contents

The Guiding Light for Chip Testing

The Wall Ahead is Made of Rubber

The Quest for Test: Will Redundancy Cover All?

Deep-Submicron MOS Transistor Matching: A Case Study

Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology

Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation

Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures

Computation of a nonlinear squashing function in digital neural networks

An Integrated Input Encoding and Symbolic Functional Decomposition for LUT-Based FPGAs

Portable Measurement Equipment for Continuous Biomedical Monitoring using Microelectrodes

Design of Erasure Codes for Digital Multimedia Transmitting

Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations

Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling

Gain reduction by gate-leakage currents in regulated cascodes

A Trapezoidal Approach to Corner Stitching Data Structures for Arbitrary Routing Angles

Continuous-Time Common-Mode Feedback Circuit for Applications with Large Output Swing and High Output Impedance

A Spread-Spectrum Clock Generator Using Fractional-N PLL Controlled Delta-Sigma Modulator for Serial-ATA III

Incremental SAT Instance Generation for SAT-based ATPG

Concurrent Error Detection for Combinational Logic Blocks Implemented with Embedded Memory Blocks of FPGAs

Analysis of the influence of intermittent faults in a microcontroller

Mapping of 40 MHz MIMO SDM-OFDM Baseband Processing on Multi-Processor SDR Platform

Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC

Rapid Prototyping of NoC Architectures from a SystemC Specification

Novel Hardware Implementation of Adaptive Median Filters

A New Design Technique for Weakly Indicating Function Blocks

Fast Boolean Minimizer for Completely Specified Functions

The HDL and FE Thermal Modeling of Heterogeneous Systems

A System-On-Chip for Wireless Body Area Sensor Network Node

Mixed-Signal DFT for fully testable ASIC

On Minimizing RTOS Aperiodic Tasks Server Energy Consumption

Boolean Formalisation of the PMC Model for Faulty Units Diagnosis in Regular Multi-Processor Systems

A Dual-Threaded Architecture for Interval Arithmetic Coprocessor with Shared Floating Point Units

Design of Time-to-Digital Converter Output Interface

Design and Simulation of Runtime Reconfigurable Systems

Modeling and observing the jitter in ring oscillators implemented in FPGAs

Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator

Various MDCT implementations in 0.35μ CMOS

Low-Voltage Low-Power Highly Linear Down-Sampling Mixer in 65nm Digital CMOS Technology

Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs

Implementation of Dynamically Reconfigurable Test Architecture for FPGA Circuits

A Partial Scan Based Test Generation for Asynchronous Circuits

Efficient Allocation of Verification Resources using Revision History Information

Ad-Hoc Translations to Close Verilog Semantics Gap

Code Coverage Analysis using High-Level Decision Diagrams

Probabilistic Model Checking and Reliability of Results

Network Probe for Flexible Flow Monitoring

NetCOPE: Platform for Rapid Development of Network Applications

IP-based Systematic Design of Power-and Matching-limited Circuits

A Low Leakage Non-Volatile Memory Voltage Pulse Generator for RFID Applications

Calculating the fault coverage for dual neighboring faults using single stuck-at fault patterns

Evaluation of the Iddq Signature in devices with Gauss-distributed background current

Interconnect Faults Identification and Localization Using Modified Ring LFSRs

Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology

Diagnosis of Realistic Defects Based on the X-Fault Model

Improving Fault Tolerance by Using Reconfigurable Asynchronous Circuits

Web-Based Framework for Parallel Distributed Test

Calculation of LFSR Seed and Polynomial Pair for BIST Applications

Excitation optimization in fault diagnosis of analog electronic circuits

Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform

Efficient Estimation of Die-Level Process Parameter Variations via the EM-Algorithm

Experimental Analog Circuit for Parametric Test Methods Efficiency Evaluation

The Influence of Global Parametric Faults on Analogue Electronic Circuits Time Domain Response Features

A novel method for test and calibration of capacitive accelerometers with a fully electrical setup

On-chip Integration of Magnetic Force Sensing Current Monitors

A Cost Effective BIST Second-Order Σ-Δ Modulator

SoC Symbolic Simulation: a case study on delay fault testing

SoCECT: System on Chip Embedded Core Test

Optimal Backgrounds Selection for Multi Run Memory Testing

Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

Incremental SAT Instance Generation for SAT-based ATPG

Content Provider	IEEE Xplore Digital Library
Author	Tille, D. Drechsler, R.
Copyright Year	2008
Description	Author affiliation: Inst. of Comput. Sci., Univ. of Bremen, Bremen (Tille, D.; Drechsler, R.)
Abstract	Due to ever increasing design sizes more efficient tools for automatic test pattern generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. This paper makes two contributions. Firstly, we analyze the two steps SAT-based ATPG consists of with respect to their run time on industrial benchmarks. Secondly, exploiting these analysis results, we propose an incremental solving technique with the objective to speed up the entire classification process. An experimental evaluation of the proposed method shows a significant reduction of the overall run time of the SAT- based ATPG process.
Starting Page	1
Ending Page	6
File Size	1450202
Page Count	6
File Format	PDF
ISBN	9781424422760
DOI	10.1109/DDECS.2008.4538759
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-16
Publisher Place	Slovakia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Circuit faults Circuit testing Test pattern generators Production Computer science Benchmark testing Tellurium Design automation Automatic control
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in