NDLI: Modeling and observing the jitter in ring oscillators implemented in FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Valtchanov, B. Aubert, A. Bernard, F. Fischer, V.
Copyright Year	2008
Description	Author affiliation: Lab. Hubert Curien, Univ. Jean Monnet, St. Etienne (Valtchanov, B.; Aubert, A.; Bernard, F.; Fischer, V.)
Abstract	Random number generators represent one of basic cryptographic primitives used to compose cryptographic protocols. While field programmable gate arrays (FPGAs) are well suited for implementing algorithmic random number generators (pseudo-random number generators), generating fast and secured true random bitstreams inside FPGAs is an open problem. Most of true random number generators in FPGAs employ the timing jitter present in ring oscillator clocks as a source of randomness. The paper analyses the jitter generated in ring oscillators and presents a simple physical model of its sources. The jitter generated in MATLAB in accordance with the proposed model is then used as an input in VHDL simulations. To evaluate the model, we use an embedded technique of jitter measurement. The principle is simulated in VHDL and validated by experiments using different FPGA technologies.
Starting Page	1
Ending Page	6
File Size	3643116
Page Count	6
File Format	PDF
ISBN	9781424422760
DOI	10.1109/DDECS.2008.4538777
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-16
Publisher Place	Slovakia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Jitter Ring oscillators Field programmable gate arrays Random number generation Cryptography Clocks Mathematical model Inverters Cryptographic protocols Security
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs

Observing the Randomness in RO-Based TRNG

FPGA Vendor Agnostic True Random Number Generator

Optimizing Speed of a True Random Number Generator in FPGA by Spectral Analysis

Random numbers generation: Investigation of narrowtransitions suppression on FPGA

Enhancing security of ring oscillator-based trng implemented in FPGA

Fast True Random Generator in FPGAs

Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs

Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Modeling and observing the jitter in ring oscillators implemented in FPGAs

Similar Documents

Characterization of randomness sources in ring oscillator-based true random number generators in FPGAs

Observing the Randomness in RO-Based TRNG

FPGA Vendor Agnostic True Random Number Generator

Optimizing Speed of a True Random Number Generator in FPGA by Spectral Analysis

Random numbers generation: Investigation of narrowtransitions suppression on FPGA

Enhancing security of ring oscillator-based trng implemented in FPGA

Fast True Random Generator in FPGAs

Influence of Magnetic Fields and X-Radiation on Ring Oscillators in FPGAs

Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings

Modeling and observing the jitter in ring oscillators implemented in FPGAs