NDLI: Shared resources high-level modeling in embedded systems using virtual nodes

Content Provider	IEEE Xplore Digital Library
Author	Jaber, C. Kanstein, A. Apvrille, L. Baghdadi, A. Pacalet, R.
Copyright Year	2009
Description	Author affiliation: Institut Telecom; Telecom Bretagne; Technopôle Brest Iroise, CS83818, 29238 Brest, France (Baghdadi, A.) \|\| Freescale Semiconductor, 134 Av. du Général Eisenhower, BP 72329, 31023 Toulouse Cedex 1, France (Jaber, C.; Kanstein, A.) \|\| Institut Telecom; Telecom ParisTech; B.P. 193, 2229 rte des Crêtes, 06904 Sophia-Antipolis Cedex, France (Apvrille, L.; Pacalet, R.)
Abstract	The increasing complexity of system-on-chip design and shorter time to market constraints has stimulated systems designers to investigate performance characteristics of the final system implementation in the early design stages, by means of modeling the design at a high level of abstraction. This paper presents the virtual node concept for modeling the shared resources of a system-on-chip, therefore specifically dedicated to the study of the impact of shared resources contention on the overall system's performance, which is often defined by concurrent use cases. The overall approach is based on using a specific UML modeling profile and a SystemC-based simulator to execute models and analyze their performance.
Starting Page	1
Ending Page	4
File Size	261007
Page Count	4
File Format	PDF
ISBN	9781424445738
DOI	10.1109/NEWCAS.2009.5290506
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-28
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded system Telecommunications System-on-a-chip Scheduling System performance Delay Time to market Unified modeling language Analytical models Performance analysis
Content Type	Text
Resource Type	Article

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