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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kawai, K. Kawahara, A. Yasuhara, R. Muraoka, S. Wei, Z. Azuma, R. Tanabe, K. Shimakawa, K. |
| Copyright Year | 2014 |
| Description | Author affiliation: Panasonic Corp., Nagaokakyo, Japan (Kawai, K.; Kawahara, A.; Yasuhara, R.; Muraoka, S.; Wei, Z.; Azuma, R.; Tanabe, K.; Shimakawa, K.) |
| Abstract | ReRAM is increasingly being developed for applications that require higher speeds and lower voltages than flash memory. We have found TaOx to have high performance and high reliability. However one of the phenomena observed in ReRAM is that each resistance after Set and Reset varies during every cycle. To stabilize resistive switching, the key is to limit these variations in resistance. In ReRAM, a conductive filament (CF) is created by the forming pulse. Resistive switching in the CF is based on reduction and oxidization using this voltage pulse. This paper reviews a hopping percolation model which we have proposed for the switching process, and this paper proposes an automatic forming circuit using our newly-developed externally-scalable forming pulse (ESF) scheme. In this CF model, conductive paths show different conductivities caused by the formation of different percolation networks that link hopping sites. Larger CFs show greater variation in resistance due to the many possible combinations of percolation networks. This makes it important to develop a forming technique that limits CFs to their optimal size. Forming is based on dielectric breakdown, so the pulse width ranges over approximately three orders. The automatic forming circuit detects, bit by bit, whether forming is over, and stops the forming pulse after a specified period. A forming pulse is then generated, using an external clock, to cover the range of pulse widths. This allows the filament size to be controlled to ensure it is uniform for all of the bits in the circuit, at the cost of only a small area overhead. |
| Sponsorship | IEEE Central Texas Sect. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 853633 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479921539 |
| DOI | 10.1109/ICICDT.2014.6838600 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Switches Resistance Clocks Reliability Integrated circuit modeling Materials Arrays Automatic Forming ReRAM TaOx Conductive Filament Hopping Percolation Model |
| Content Type | Text |
| Resource Type | Article |
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