NDLI: A comparative analysis of 3D-IC partitioning schemes for asynchronous circuits

Content Provider	IEEE Xplore Digital Library
Author	Caley, L. Chien-Wei Lo Sabado, F. Jia Di
Copyright Year	2014
Description	Author affiliation: Comput. Sci. & Comput. Eng. Dept., Univ. of Arkansas Fayetteville, Fayetteville, AR, USA (Caley, L.; Chien-Wei Lo; Sabado, F.; Jia Di)
Abstract	In an attempt to further extend Moore's Law, circuit designers are turning to three-dimensional integrated circuit (3D-IC) design. However, stacking active devices presents new design challenges, the most notable being thermal dissipation. When paired with a delay-insensitive asynchronous circuit design technique such as NULL Convention Logic (NCL), the two technologies unite to solve the inherent weaknesses of each other. As part of the 3D-IC design process, a circuit must be partitioned evenly between the stacked wafers. This study presents three strategies to split an NCL circuit into two die, in an attempt to discover the optimal partitioning method for asynchronous circuits. Analysis is done on total interconnect length, number of thru-silicon vias required, and circuit area.
Sponsorship	IEEE Central Texas Sect.
Starting Page	1
Ending Page	4
File Size	2808143
Page Count	4
File Format	PDF
ISBN	9781479921539
DOI	10.1109/ICICDT.2014.6838586
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit interconnections Pipelines Three-dimensional displays Through-silicon vias Asynchronous circuits Stacking Logic gates NULL Convention Logic Delay-Insensitive Asynchronous Logic 3D-IC Partitioning
Content Type	Text
Resource Type	Article

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