NDLI: CMOS stress sensor for 3D integrated circuits: Thermo-mechanical effects of Through Silicon Via (TSV) on surrounding silicon

Content Provider	IEEE Xplore Digital Library
Author	Ewuame, K.A. Fiori, V. Inal, K. Bouchard, P.-O. Gallois-Garreignot, S. Lionti, S. Tavernier, C. Jaouen, H.
Copyright Year	2014
Description	Author affiliation: CEMEF, Mines ParisTech, Sophia Antipolis, France (Inal, K.; Bouchard, P.-O.) \|\| STMicroelectron., Crolles, France (Ewuame, K.A.; Fiori, V.; Gallois-Garreignot, S.; Lionti, S.; Tavernier, C.; Jaouen, H.)
Abstract	This work aims at determining thermomechanical stresses induced by annealed copper filled Through Silicon Via (TSV) in single crystalline silicon by using MOS (Metal Oxide Semiconductor) rosette sensors. These sensors were specifically designed and embedded. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on test vehicle. The MOS stress sensors would have been needed to be calibrated: first results of the calibration were obtained however, since they were still partial, they were not used to make the bridge from electric to mechanic quantities. Experimental findings were based on the direct calculation of stresses from electrical measurements data and literature piezoresistive coefficients. In order to get only the TSV contribution and to suppress the manufacturing process variability contribution, an optimization calculation was needed. A finite element approach was also adopted to evaluate numerically the stresses induced by TSV. The stress values obtained from the optimization are in the range of the ones obtained by simulation in the sensor area. Thus, it can be stated that the methodology is relevant, and the results will be confirmed by extracting the true piezoresistive coefficients for the embedded MOS. Once calibration performed, the piezoresistive coefficients should enable getting more accurate stress values. At this stage, the quite good agreement between numerical and experimental results seems promising.
Sponsorship	Philips
Starting Page	1
Ending Page	8
File Size	1724433
Page Count	8
File Format	PDF
e-ISBN	9781479947904
DOI	10.1109/EuroSimE.2014.6813808
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-07
Publisher Place	Belgium
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS integrated circuits Silicon Abstracts Calibration Q measurement Through-silicon vias
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Impact of TSV induced thermo-mechanical stress on semiconductor device performance

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Thermomechanical reliability of through-silicon vias in 3D interconnects

Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

3D integration of standard integrated circuits

Study of 3D process impact on advanced CMOS devices

TSV-annealing: A thermo-mechanical assessment

The impact of through silicon via proximity on CMOS device

CMOS stress sensor for 3D integrated circuits: Thermo-mechanical effects of Through Silicon Via (TSV) on surrounding silicon

Similar Documents

Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Impact of TSV induced thermo-mechanical stress on semiconductor device performance

3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Thermomechanical reliability of through-silicon vias in 3D interconnects

Practical implications of via-middle Cu TSV-induced stress in a 28nm CMOS technology for Wide-IO logic-memory interconnect

3D integration of standard integrated circuits

Study of 3D process impact on advanced CMOS devices

TSV-annealing: A thermo-mechanical assessment

The impact of through silicon via proximity on CMOS device

CMOS stress sensor for 3D integrated circuits: Thermo-mechanical effects of Through Silicon Via (TSV) on surrounding silicon