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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ben Ooi Zee Min Wong Chee Ling Hoh Cheng Wei Leong Bi Jun |
| Copyright Year | 2012 |
| Description | Author affiliation: Mini-Circuits Technologies (M) Sdn Bhd (Ben Ooi Zee Min; Wong Chee Ling; Hoh Cheng Wei; Leong Bi Jun) |
| Abstract | A method of biasing low noise amplifiers using the concept of overdrive voltage, V is introduced. The RF parameters of different FET sizes are measured against V to determine the optimum biasing points for good noise figure and OIP3. It was determined that the best biasing for low noise figures is between 0.15 to 0.25V and for OIP3 is 0.28 to 0.32V. Through careful selection of the biasing architecture, this concept is then applied to the design of a low noise amplifier employing a source degeneration technique. This resulted in the design of Mini-Circuit's PSA4–5043+ broadband low noise MMIC amplifier which is internally matched and having a typical noise figure of 0.65dB at 1 GHz and 0.9dB at 4GHz using a 0.5um pHEMT process. |
| Starting Page | 1 |
| Ending Page | 10 |
| File Size | 471208 |
| Page Count | 10 |
| File Format | |
| ISBN | 9781467301299 |
| e-ISBN | 9781467301305 |
| e-ISBN | 9781467301282 |
| DOI | 10.1109/WAMICON.2012.6208470 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-04-15 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Noise Logic gates Mirrors Noise figure Resistors PHEMTs |
| Content Type | Text |
| Resource Type | Article |
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