NDLI: High-Speed Parallel Architecture for Software-Based CRC

Content Provider	IEEE Xplore Digital Library
Author	Youngju Do Sung-Rok Yoon Taekyu Kim Kwang Eui Pyun Sin-Chong Park
Copyright Year	2008
Description	Author affiliation: Inf. & Commun. Univ., Daejeon (Youngju Do; Sung-Rok Yoon; Taekyu Kim; Kwang Eui Pyun; Sin-Chong Park)
Abstract	This paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called 'N-byte RCC (Repetition of Computation and Combination)''. This algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the 'zero block lookup tables'. This algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.
Starting Page	74
Ending Page	78
File Size	397285
Page Count	5
File Format	PDF
ISBN	9781424414567
e-ISBN	9781424414574
DOI	10.1109/ccnc08.2007.23
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel architectures Cyclic redundancy check Computer architecture Software algorithms Iterative algorithms Network-on-a-chip Concurrent computing Table lookup Network topology Parallel algorithms
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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