NDLI: Equivalence checking for synchronous elastic circuits

Content Provider	IEEE Xplore Digital Library
Author	Wijayasekara, V. Srinivasan, S.K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., North Dakota State Univ., Fargo, ND, USA (Wijayasekara, V.; Srinivasan, S.K.)
Abstract	Synchronous elastic circuits are clock-based latency insensitive circuits. Elastic circuits are typically synthesized from synchronous circuits. After synthesis, additional buffers can be arbitrarily inserted in the data path of an elastic circuit without altering its functionality to resolve timing issues. We have developed a verification tool that can check the equivalence of an elastic circuit (even after the inclusion of any number arbitrarily placed additional buffers) with its synchronous parent circuit. The tool inputs elastic circuits in VHDL. We have developed an algorithm that automatically computes efficient mapping functions used to map elastic circuit states with states of the synchronous parent circuit. Such mapping functions (required for equivalence checking) can be challenging to compute automatically, as the inclusion of additional buffers can drastically alter the pattern of data flow through the circuit. The capacity of the equivalence checker is demonstrated with results from 24 elastic circuit benchmarks, many of which have over 100,000 gates and 1,000 latches.
Starting Page	109
Ending Page	118
File Size	224441
Page Count	10
File Format	PDF
ISBN	9781479909032
e-ISBN	9781479909056
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	IP networks Synchronization Benchmark testing Protocols Latches Wires refinement latency insensitive / elastic circuits equivalence checking
Content Type	Text
Resource Type	Article

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