NDLI: Keynote talk II: Designing tomorrow's chips

Content Provider	IEEE Xplore Digital Library
Author	Hoskote, Y.
Copyright Year	2013
Abstract	Next generation systems in such domains as wearables and Internet of Things will have capabilities for sensing, recognition and intelligence. Such systems integrate multiple hardware components - including sensors, actuators, compute and commumcations modules - together with complex software in an ultra-low power envelope. This talk will explore the needs of a design environment that is required to rapidly design such systems. A top down model-based design methodology that follows a refinement based approach will leverage such a design environment. Many of the pieces exist today at various levels of maturity, but there remain gaps that need to be addressed.
Starting Page	75
Ending Page	76
File Size	2185188
Page Count	2
File Format	PDF
ISBN	9781479909032
e-ISBN	9781479909056
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Next generation networking Sensors System-on-chip IP networks Chip scale packaging Computers Awards activities
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Keynote talk II: Designing tomorrow's chips