NDLI: Multi-dimensional Evaluation of Haswell's Transactional Memory Performance

Content Provider	IEEE Xplore Digital Library
Author	Machado Pereira, M. Gaudet, M. Amaral, J.N. Araujo, G.
Copyright Year	2014
Description	Author affiliation: Comput. Sci. Dept., Univ. of Alberta, Edmonton, AB, Canada (Gaudet, M.; Amaral, J.N.) \|\| Inst. of Comput., UNICAMP, Campinas, Brazil (Machado Pereira, M.; Araujo, G.)
Abstract	This paper presents an extensive performance study of the implementation of Hardware Transactional Memory (HTM) in the Haswell generation of Intel x86 core processors. This study evaluates the strengths and weaknesses of this new architecture exploring several dimensions in the space of Transactional Memory (TM) application characteristics using the Eigenbench [1] and the CLOMP-TM [2] benchmarks. This detailed performance study provides insights on the constraints imposed by the Intel's Transaction Synchronization Extension (Intel's TSX) and introduces a simple, but efficient policy for guaranteeing forward progress on top of the besteffort Intel's HTM and also was critical to achieving performance. The evaluation also shows that there are a number of potential improvements for designers of TM applications and software systems that use Intel's TM and provides recommendations to extract maximum benefit from the current TM support available in Haswell.
Starting Page	144
Ending Page	151
File Size	323325
Page Count	8
File Format	PDF
ISBN	9781479969050
ISSN	15506533
DOI	10.1109/SBAC-PAD.2014.33
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Benchmark testing Pollution Software Registers Synchronization Buffer storage
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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