NDLI: Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems

Content Provider	IEEE Xplore Digital Library
Author	Andrade, G. Ferreira, R. Teodoro, G. Rocha, L. Saltz, J.H. Kurc, T.
Copyright Year	2014
Description	Author affiliation: Fed. Univ. of Minas Gerais, Belo Horizonte, Brazil (Andrade, G.; Ferreira, R.) \|\| Fed. Univ. of Sao Joao del Rei, Sao Joao del Rei, Brazil (Rocha, L.) \|\| Stony Brook Univ., Stony Brook, NY, USA (Saltz, J.H.; Kurc, T.) \|\| Univ. of Brasilia, Brasilia, Brazil (Teodoro, G.)
Abstract	High performance computing is experiencing a major paradigm shift with the introduction of accelerators, such as graphics processing units (GPUs) and Intel Xeon Phi (MIC). These processors have made available a tremendous computing power at low cost, and are transforming machines into hybrid systems equipped with CPUs and accelerators. Although these systems can deliver a very high peak performance, making full use of its resources in real-world applications is a complex problem. Most current applications deployed to these machines are still being executed in a single processor, leaving other devices underutilized. In this paper we explore a scenario in which applications are composed of hierarchical dataflow tasks which are allocated to nodes of a distributed memory machine in coarse-grain, but each of them may be composed of several finer-grain tasks which can be allocated to different devices within the node. We propose and implement novel performance aware scheduling techniques that can be used to allocate tasks to devices. We evaluate our techniques using a pathology image analysis application used to investigate brain cancer morphology, and our experimental evaluation shows that the proposed scheduling strategies significantly outperforms other efficient scheduling techniques, such as Heterogeneous Earliest Finish Time - HEFT, in cooperative executions using CPUs, GPUs, and Masc. also experimentally show that our strategies are less sensitive to inaccuracy in the scheduling input data and that the performance gains are maintained as the application scales.
Starting Page	89
Ending Page	96
File Size	1238482
Page Count	8
File Format	PDF
ISBN	9781479969050
ISSN	15506533
DOI	10.1109/SBAC-PAD.2014.15
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microwave integrated circuits Graphics processing units Performance evaluation Processor scheduling Central Processing Unit Image analysis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Accelerating Large Scale Image Analyses on Parallel, CPU-GPU Equipped Systems

Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems

High-throughput Analysis of Large Microscopy Image Datasets on CPU-GPU Cluster Platforms

Comparative Performance Analysis of Intel (R) Xeon Phi (TM), GPU, and CPU: A Case Study from Microscopy Image Analysis

A Study with MIC-GPU-CPU Heterogeneous Architecture in Electrocardiograms Simulation of Electrocardiogram Based Whole-Heart Model

Speed-up image processing on mobile CPU and GPU

Scheduling Concurrent Applications on a Cluster of CPU-GPU Nodes

Performance comparison of CPU and GPU on a discrete heterogeneous architecture

CPU+GPU Programming of Stencil Computations for Resource-Efficient Use of GPU Clusters

Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems

Similar Documents

Accelerating Large Scale Image Analyses on Parallel, CPU-GPU Equipped Systems

Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems

High-throughput Analysis of Large Microscopy Image Datasets on CPU-GPU Cluster Platforms

Comparative Performance Analysis of Intel (R) Xeon Phi (TM), GPU, and CPU: A Case Study from Microscopy Image Analysis

A Study with MIC-GPU-CPU Heterogeneous Architecture in Electrocardiograms Simulation of Electrocardiogram Based Whole-Heart Model

Speed-up image processing on mobile CPU and GPU

Scheduling Concurrent Applications on a Cluster of CPU-GPU Nodes

Performance comparison of CPU and GPU on a discrete heterogeneous architecture

CPU+GPU Programming of Stencil Computations for Resource-Efficient Use of GPU Clusters

Efficient Execution of Microscopy Image Analysis on CPU, GPU, and MIC Equipped Cluster Systems