NDLI: The bank-overlapped post-Doppler method and its system design for self-developed parallel processing boards

Content Provider	IEEE Xplore Digital Library
Author	Suzuki, J. Yamada, H. Yamaguchi, Y. Tanabe, M.
Copyright Year	2008
Description	Author affiliation: Komukai Oper., Toshiba Corp., Kawasaki (Suzuki, J.; Tanabe, M.) \|\| Fac. of Eng., Niigata Univ., Niigata (Yamada, H.; Yamaguchi, Y.)
Abstract	Post-Doppler methods are rank reduction techniques to reduce temporal dimensions by applying the Doppler filter and can reduce the processing time than full degrees-of-freedom (DOF) space-time adaptive processing (STAP). In post-Doppler methods, multi-bin post-Doppler methods are generally used to improve the performance of signal-to-interference-plus-noise ratio (SINR). However, it is necessary to solve the issue of different adaptation for each Doppler bin by using the covariance matrices which formed by multiple filter banks. Therefore, it is very effective to calculate each optimum weight in parallel. For further improvements of processing time, we propose an efficient approach to calculate not one but multiple Doppler bins. When a uniform filter weight is applied to the proposed method, the performance of SINR deteriorate in the vicinity of bank edges. Therefore, we improved the performance by overlapping in the filter bank of both ends. In addition, we show its system design and benchmark results by using self-developed digital signal processor (DSP) boards.
Starting Page	1
Ending Page	5
File Size	245021
Page Count	5
File Format	PDF
ISBN	9781424415380
ISSN	10975659
DOI	10.1109/RADAR.2008.4720941
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Filter bank Covariance matrix Digital signal processing Adaptive filters Signal to noise ratio Filtering Nonlinear filters Digital signal processors Field programmable gate arrays STAP post-Doppler methods bank-overlapped
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

"Optimum" filter for speech enhancement using integrated digital signal processors

Microphone Array Speech Enhancement Based on Filter Bank Generalized Sidelobe Canceller

FPGA implementation of vector directional distance filter

Improved pre-Doppler STAP algorithm for adaptive clutter nulling in airborne radars

A Partial Self-Reconfigurable Adaptive FIR Filter System

Autoassociative neural networks and noise filtering

Post pulse compression and partially adaptive multi-waveform STAP

The Implementation of a High Speed Adaptive FIR Filter on a Field Programmable Gate Array

FPGA approach of an adaptive filter for ECG signal processing

The bank-overlapped post-Doppler method and its system design for self-developed parallel processing boards

Similar Documents

"Optimum" filter for speech enhancement using integrated digital signal processors

Microphone Array Speech Enhancement Based on Filter Bank Generalized Sidelobe Canceller

FPGA implementation of vector directional distance filter

Improved pre-Doppler STAP algorithm for adaptive clutter nulling in airborne radars

A Partial Self-Reconfigurable Adaptive FIR Filter System

Autoassociative neural networks and noise filtering

Post pulse compression and partially adaptive multi-waveform STAP

The Implementation of a High Speed Adaptive FIR Filter on a Field Programmable Gate Array

FPGA approach of an adaptive filter for ECG signal processing

The bank-overlapped post-Doppler method and its system design for self-developed parallel processing boards