NDLI: VLSI-architecture for enabling multiple parallel associative searches with standard SRAM macros

Content Provider	IEEE Xplore Digital Library
Author	Kumaki, T. Imai, Y. Koide, T. Mattausch, H.J.
Copyright Year	2009
Description	Author affiliation: Research Institute for Nanodevices and Bio Systems, Hiroshima University, Japan (Kumaki, T.; Imai, Y.; Koide, T.; Mattausch, H.J.)
Abstract	This paper presents a ternary multi-ported content addressable memory (CAM) architecture utilizing asynchronous multiple search-operation technology, aiming at efficient high throughput of associative-search operations. The asynchronous multiple search-operation technology adopts a Flexible Multi-ported Content Addressable Memory (FMCAM) architecture, which is reported in [1], [2]. The proposed ternary multi-ported CAM architecture achieves a fast associative table-lookup solution for high-speed routing applications, such as IP packet forwarding and effectively realizes a Ternary Flexible Multi-ported Content Addressable Memory which we refer to as TFMCAM in this paper. The main novel points of the architecture are simultaneous multiple associative-search operations and a high implementation-yield ratio. The TFMCAM can fully exploit the conventional SRAM memory architecture in comparison to the conventional TCAM architecture. Furthermore, the TFMCAM architecture realizes the necessary background table maintenance function without preventing the associative-search operation. For verifying the effectiveness of the TFMCAM architecture, ASIC implementation results are evaluated in this paper.
Starting Page	45
Ending Page	48
File Size	272101
Page Count	4
File Format	PDF
ISBN	9781424450152
DOI	10.1109/ISPACS.2009.5383906
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-01-07
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Associative memory Memory architecture Computer aided manufacturing CADCAM Routing Circuits Hardware Biomedical signal processing Communication standards
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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