NDLI: Failure Mechanisms in Passivated P+ -N Junctions Under Temperature and Bias Stress

Content Provider	IEEE Xplore Digital Library
Author	Tokuyama, Takashi
Copyright Year	1966
Description	Author affiliation: Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan (Tokuyama, Takashi)
Abstract	The mechanisms for anomalous increase of reverse current by reverse bias and temperature stress treatment on silicon p+-n planar junctions are analysed in detail. The effect of surface characteristics upon junction I-V curve is first surveyed generally by preparing the samples that have MOS type gate electrode in three types of configurations. Gate voltage to junction current curves are compared before and after the stress treatment and concluded that after the stress treatment, n-type inversion layers are formed on the very confined portions of the p-type diffused layer. It is also indicated that units having high resistivity n-type diffused layer. It is also indicated that units having high resistivity n-type substrate are easily deteriorated. From these facts, it is concluded that n-type inversion layers are formed only on the p-type surface where the acceptor densities decrease by the lateral diffusion under the oxide mask. As the mechanisms for anomalous increase of reverse current, the breakdown of field induced junctions by avalanching or tunneling is already proposed, however, in our case, tunneling mechanism is difficult to expect since n-type inversion layer is only formed on the lower acceptor portions of the diffused layers as stated above. This is experimentally verified from the large temperature coefficient of the reverse current and observation of no Esaki component in the forward current.
Starting Page	244
Ending Page	264
File Size	11360827
Page Count	21
File Format	PDF
ISSN	00972088
DOI	10.1109/IRPS.1966.362366
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1966-11-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Failure analysis Temperature Stress Conductivity Tunneling Silicon Surface treatment Electrodes Voltage Electric breakdown
Content Type	Text
Resource Type	Article

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