NDLI: A 34.8%-PAE CMOS transmitter frontend for 24-GHz FMCW radar applications

Content Provider	IEEE Xplore Digital Library
Author	Huan-Sheng Chen Liang-Hung Lu
Copyright Year	2012
Description	Author affiliation: Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Huan-Sheng Chen; Liang-Hung Lu)
Abstract	A high-efficiency transmitter frontend circuit suitable for 24-GHz frequency-modulated continuous-wave (FMCW) radar applications is presented in this paper. In addition to the power amplifier (PA) stage, a voltage-controlled oscillator (VCO) is incorporated in the frontend for frequency modulation while a VCO buffer and a driving amplifier (DA) are utilized to provide an adequate driving level and reverse isolation. To take full advantage of the power available from the transistors, both the PA and DA stages are matched to the near-optimum impedances suggested by the load-pull simulation. Moreover, a positive-feedback technique is employed in the PA design for further efficiency enhancement. The proposed circuit is fabricated in a standard 90-nm CMOS process. Operated at a supply voltage of 1.2-V, the 24-GHz frontend demonstrates a peak power-added efficiency (PAE) of 34.8% with a peak output power of 16.3 dBm.
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	265
Ending Page	268
File Size	1535350
Page Count	4
File Format	PDF
DOI	10.1109/IPEC.2012.6522676
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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