NDLI: A 0.3-V all digital crystal-less clock generator for energy harvester applications

Content Provider	IEEE Xplore Digital Library
Author	Jen-Chieh Liu Wei Chun Lee Hong-Yi Huang Kuo-Hsing Cheng Chao-Jen Huang Yu-Wei Liang Jia-Hung Peng Yuan-Hua Chu
Copyright Year	2012
Description	Author affiliation: Grad. Inst. of Electr. Eng., Nat. Taipei Univ., Taipei, Taiwan (Hong-Yi Huang) \|\| Dept. of Electr. Eng., Nat. Central Univ., Chungli, Taiwan (Kuo-Hsing Cheng) \|\| Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan (Jen-Chieh Liu; Chao-Jen Huang; Jia-Hung Peng; Yuan-Hua Chu)
Abstract	A 0.3 V all digital crystal-less clock generator (CLCG) is presented for a hearing aid application. The all digital CLCG uses frequency difference between the ring oscillator and the digital controlled oscillator (DCO) to create a mapping table under process and temperature variations. The digital loop filter (DLF) adopts a successive-approximation register (SAR) algorithm for fast locking time. Thus, the worse case of locking time is 73 output cycles. For a hearing aid application, the core area of CLCG and hearing aid system are 62 × 78 $μm^{2}$ and 1900 × 1920 $μm^{2},$ respectively, in 65 nm CMOS process. The frequency accuracy is 12 MHz ±3.5% in four test chips. The power consumption is 5 μW. In the period jitter, the RMS and peak-to-peak jitters are 326.4 ps and 2.05 ns, respectively. The frequency drift is smaller than ±4.3% from 0 to 100°C. Thus, this work is also used for energy harvester applications.
Sponsorship	IEEE Solid-State Circuits Soc.
Starting Page	117
Ending Page	120
File Size	1189491
Page Count	4
File Format	PDF
DOI	10.1109/IPEC.2012.6522641
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-12
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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