NDLI: An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Content Provider	IEEE Xplore Digital Library
Author	de Carvalho, M. Bernardi, P. Sanchez, E. Reorda, M.S.
Copyright Year	2010
Abstract	Reliability characterization is the industrial process intended to measure the useful life period and failure rate of a component population by exploiting stress mechanisms. The paper describes a methodology for the automatic generation of stress programs to be used during the reliability characterization process of Systems-on-Chip (SoC). The proposed methodology is composed of a two-phase strategy, first an evolutionary algorithm (EA) works on the SoC's description at Register-Transfer-Level (RTL) by evaluating high-level metrics to quickly progress to a sufficient stress quality level, then evolution is continued on the gate-level description towards a better stress quality. The proposed methodology was experimented on a SoC manufactured in a 90nm technology including an 8051 processor. The proposed strategy reduces significantly the generation times and quickly improves the stress quality values with respect to the previous methodology.
Starting Page	29
Ending Page	34
File Size	416582
Page Count	6
File Format	PDF
ISBN	9781612842875
DOI	10.1109/MTV.2010.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Logic gates System-on-a-chip Measurement Reliability Switches Bismuth SoC Reliability Characterization Functional Stress Pattern Generation
Content Type	Text
Resource Type	Article

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