NDLI: Bounded Model Checking of Incomplete Networks of Timed Automata

Content Provider	IEEE Xplore Digital Library
Author	Miller, C. Gitina, K. Scholl, C. Becker, B.
Copyright Year	2010
Abstract	Verification of real-time systems - e.g. communication protocols or embedded controllers - is an important task. One method to detect errors is called bounded model checking (BMC). In BMC the system is iteratively unfolded and then transformed into a satisfiability problem. If an appropriate solver finds the $k$-th instance to be satisfiable a counterexample for a given safety property has been found. In this paper we present a first approach to apply BMC to networks of timed automata (that is a system of several interacting subautomata) where parts of the network are unspecified (so called blackboxes). Here, we would like to answer the question of unrealizability, that is, is there a path of a certain length violating a safety property regardless of the implementation of the blackboxes. We provide solutions to this problem for two timed automata communication models. For the simple synchronization model, a BMC approach based on fixed transitions is introduced resulting in a SAT-Modulo-Theory formula. With respect to the use of bounded integer variables for communication, we prove unrealizability by introducing universal quantification, yielding more advanced quantified SAT-Modulo-Theory formulas.
Starting Page	61
Ending Page	66
File Size	443247
Page Count	6
File Format	PDF
ISBN	9781612842875
DOI	10.1109/MTV.2010.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automata Synchronization Clocks Encoding Safety Real time systems Protocols quantified SMT BMC Timed Automata Blackbox SMT
Content Type	Text
Resource Type	Article

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