NDLI: Top Level SOC Interconnectivity Verification Using Formal Techniques

Content Provider	IEEE Xplore Digital Library
Author	Roy, S.K.
Copyright Year	2007
Description	Author affiliation: Texas Instrum. India, Bangalore (Roy, S.K.)
Abstract	SOCs are designed by integrating existing in house cores/intellectual properties (IPs), or third party core/IPs provided by external vendors to reduce design turn-around time and cost. The integration process in realizing an SOC implementation consists of several different kinds of integration which can be classified as (1) static or non-functional integration, consisting of simple electrical connections (or hookup) of the inputs and outputs of different IPs, and (2) dynamic, or functional integration, where, besides the pure electrical connectivity, a temporal and a functional dimension needs to be taken into account. Given the size of present generation SOCs there is ample scope of inadvertent design errors being introduced during the integration process. It has been observed in many in-house SOC designs that a large percentage of these errors (80%) are contributed by pure connectivity errors. Severity of implications of some of these errors, are dependent on when they are detected in the design verification cycle, and on how easy it is to correct them in the implementation. In this paper, we present the challenges involved in detecting such integration errors in complex SOCs through the use of formal verification techniques. The main contributions of this work are (1) effective use of formal techniques based on symbolic model checking in the top level verification of SOC integration, (2) effective use of abstraction and modeling of SOC sub-systems in enabling assertion based formal verification, (3) automated generation of assertions and constraints to detect integration errors, (4) automated generation of scripts to capture the SOC design information and invoke a formal verification tool on which to prove the validity or correctness of these assertions, and (5) case studies from different categories of SOC integration to highlight the benefits of the proposed approach. These techniques have been applied to verify different kinds of integration described above in several SOCs designed in Texas Instruments, with promising results.
Starting Page	63
Ending Page	70
File Size	173093
Page Count	8
File Format	PDF
ISBN	9780769532417
ISSN	15504093
DOI	10.1109/MTV.2007.22
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip IP networks Formal verification Magnetic cores Clocks Joining processes Built-in self-test Automated generation of assertions SOC Integration Top Level Inteconnectivity Formal Verification Abstraction
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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