NDLI: A motor speed control system using dual-loop PLL and speed feed-forward/back

Content Provider	IEEE Xplore Digital Library
Author	Mchida, H. Kambara, M. Tanaka, K. Kobayashi, F.
Copyright Year	2010
Description	Author affiliation: Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka, Japan (Kobayashi, F.) \|\| Maizuru national college of technology, 234 Shiroya, Kyoto, Japan (Mchida, H.; Tanaka, K.) \|\| Factory-Automation Electronics Inc., 1-6-14 dai-ni nichidai building 1F, higashinakajima, higasiyodogawa-ku, Osaka, Japan (Kambara, M.)
Abstract	PLL speed control systems can completely reject speed error and steady-state phase error for constant-speed inputs. Though it does not usually handle inputs including acceleration, the dual-loop scheme improves, as a feed-forward control system, rising time and phase error for acceleration input. However, since it is fundamentally a third-order PLL, it has slow rising up characteristics than speed feed-back, and cannot avoid over/undershoots. Nonetheless, the first loop has rapid rising up characteristics and no over/undershoot, since it is an ideal second-order PLL system. In this article, to solve the problem, we show a hybrid system of the dual-loop PLL and speed feed-forward/back. It has fast rising up characteristics and no over/undershoots thanks to the first and third PLL as F/V converter, which cannot be achieved in traditional PLL systems.
Starting Page	1512
Ending Page	1517
File Size	412077
Page Count	6
File Format	PDF
ISBN	9781424451401
ISSN	2152744X
DOI	10.1109/ICMA.2010.5588283
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-08-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops Voltage-controlled oscillators Acceleration DC motors Lead Velocity control Phase frequency detector
Content Type	Text
Resource Type	Article

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