NDLI: FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

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2015 25th International Conference on Field Programmable Logic and Applications (FPL)

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

2013 23rd International Conference on Field programmable Logic and Applications

22nd International Conference on Field Programmable Logic and Applications (FPL)

2011 21st International Conference on Field Programmable Logic and Applications

Table of Contents

General Chair Message

A Note from the Program Chairs

Program Committee

Steering Committee

Additional Reviewers

Accelerating Image Analysis for Localization Microscopy with FPGAs

Unifying Finite Difference Option-Pricing for Hardware Acceleration

Leros: A Tiny Microcontroller for FPGAs

Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC Inverters

A New Process Characterization Method for FPGAs Based on Electromagnetic Analysis

An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors

A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs

Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory

An FPGA Solver for SAT-Encoded Formal Verification Problems

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities

Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms

Latch-Based Performance Optimization for FPGAs

XDL-Based Module Generators for Rapid FPGA Design Implementation

Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks

A Radix Tree Router for Scalable FPGA Networks

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks

20Gbps C-Based Complex Event Processing

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method

A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations

Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware Compilation

Implementing Stream-Processing Applications on FPGAs: A DSL-Based Approach

Revisiting the Newton-Raphson Iterative Method for Decimal Division

Hardware Support for Broadcast and Reduce in MPSoC

The Impact of Aging on an FPGA-Based Physical Unclonable Function

An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators

Multi-module Hashing System for SHA-3 & FPGA Integration

FPGA-Accelerated Object Detection Using Edge Information

Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware

RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC

Memory Virtualization for Multithreaded Reconfigurable Hardware

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures

ERDB: An Embedded Routing Database for Reconfigurable Systems

Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGA

Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule Enforcement

Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGA

An Implementation of the Mean Shift Filter on FPGA

Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs

FPGA-Specific Arithmetic Optimizations of Short-Latency Adders

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs

FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric

VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic

A Dynamically-Reconfigurable Phased Array Radar Processing System

Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case

A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware

A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values

Stress-Aware Module Placement on Reconfigurable Devices

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms

A Routing Architecture for Mapping Dataflow Graphs at Run-Time

An Easily Testable Routing Architecture and Efficient Test Technique

Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs

Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

A Model for Matrix Multiplication Performance on FPGAs

Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA

High Frequency Trading Acceleration Using FPGAs

Improving FPGA Reliability with Wear-Levelling

A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAs

Reducing FPGA Router Run-Time through Algorithm and Architecture

Fast RTL Power Estimation for FPGA Designs

RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy Considerations

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Compact Hardware Architecture for Hummingbird Cryptographic Algorithm

Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC

Failure Probability and Fault Observability of SRAM-FPGA Systems

FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control

Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node

Real-Time Evaluation of Remote Sensing Data on Board of Satellites

Heterogeneous Platform for Stream Based Applications on FPGAs

Implementation in FPGA of Address-Based Data Sorting

Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification Tree

FPGA Acceleration of the Phylogenetic Parsimony Kernel?

Timing-Driven Routing of High Fanout Nets

Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs

Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign

A Radiation Hard Lut Block with Auto-Scrubbing

FPGA Interconnect Architecture Exploration Based on a Statistical Model

Capacitive Boosting for FPGA Interconnection Networks

Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time

Synthesizing Tiled Matrix Decomposition on FPGAs

Acceleration of Multi-agent Simulation on FPGAs

Molecular Docking on FPGA and GPU Platforms

Pattern Compression of FAST Corner Detection for Efficient Hardware Implementation

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs

Resource Management for the Heterogeneous Arrays of Hardware Accelerators

A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine

Remote FPGA Lab with Interactive Control and Visualisation Interface

Cryptographic Extension for Soft General-Purpose Processors with Secure Key Management

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs

Compact CLEFIA Implementation on FPGAS

Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug

Speculative Debug Insertion for FPGAs

Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems

On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry

Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking

Optimizing an Open-Source Processor for FPGAs: A Case Study

Publisher's Information

2010 International Conference on Field Programmable Logic and Applications

2009 International Conference on Field Programmable Logic and Applications

2008 International Conference on Field Programmable Logic and Applications

2007 International Conference on Field Programmable Logic and Applications

2006 International Conference on Field Programmable Logic and Applications

International Conference on Field Programmable Logic and Applications, 2005.

FPGA-Based Acceleration of Block Matching Motion Estimation Techniques

Content Provider	IEEE Xplore Digital Library
Author	Gonzalez, D. Botella, G. Mokheerje, S. Meyer-Base, U.
Copyright Year	2011
Abstract	This paper focuses on the hardware acceleration of Block Matching motion estimation techniques (Search reduction family) suitable for the standard H.264/AVC MPEG-4 part 10 video compression. Many representative motion estimation search algorithms are explained here. As hardware, the well known Altera DE2 platform with a Cyclone II EP2C35F672C6 is used with a soft core NIOS II processor. C2H compiler which permits us to speed up the system at least two magnitude order is used to accelerate our source code. The paper shows the results in terms of performance and resources needed. This is the starting point to accelerate motion estimation algorithms using many strategies considering an ad-hoc motion estimation processor.
Starting Page	389
Ending Page	392
File Size	1949871
Page Count	4
File Format	PDF
ISBN	9781457714849
DOI	10.1109/FPL.2011.76
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Hardware Motion estimation Field programmable gate arrays Throughput Transform coding Educational institutions Embedded Systems Optical Flow MPEG Compression Block Matching algorithm NIOS II FPGA
Content Type	Text
Resource Type	Article

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