NDLI: Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Content Provider	IEEE Xplore Digital Library
Author	Otero, A. De La Torre, E. Riesgo, T. Cervero, T. Lopez, S. Callico, G. Sarmiento, R.
Copyright Year	2011
Abstract	Systems relying on fixed hardware components with a static level of parallelism can suffer from an under use of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macro block (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly.
Starting Page	369
Ending Page	375
File Size	690303
Page Count	7
File Format	PDF
ISBN	9781457714849
DOI	10.1109/FPL.2011.72
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-05
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Filtering Scalability Arrays Parallel processing Static VAr compensators Field programmable gate arrays SVC Reconfigurable architectures scalable architecture Deblocking Filter H.264/AVC
Content Type	Text
Resource Type	Article

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