NDLI: Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Milojevic, D. Radojcic, R. Carpenter, R. Marchal, P.
Copyright Year	2009
Description	Author affiliation: Javelin DA, Suite 118-IMEC, 21028 Bank Mill Road-Kapeldreef 75, Saratoga, CA 95070-B-3001 Leuven, USA-Belgium (Carpenter, R.; Marchal, P.) \|\| ULB, BEAMS, CP165/57-Qualcomm Inc., 50, Av.F. Roosevelt-5775 Morehouse Dr, B-1050, Brussels-San Diego, CA 92121, Belgium-USA (Milojevic, D.; Radojcic, R.)
Abstract	This paper introduces new design methodology and the corresponding EDA tool chain enabling fast design space exploration and high fidelity of results for emerging heterogeneous 3D-Stacked Integrated Circuits. The proposed framework allows designers to easily trade-off between different system level design choices (e.g. functional partitioning), physical design options (e.g. packaging strategies) and/or technology options (e.g. different technology nodes) and understand their impact on typical design parameters such as cost, performance and power. We demonstrate the proposed framework using existing MPSoC for video coding applications. The system is virtually prototyped as traditional 2D and then 3D design. For a 3D version we place the off-chip DRAM memory on the top of the processing die, and consider different packaging options. For different implementation scenarios we quantify typical design parameters showing the benefits of the 3D integration.
Starting Page	118
Ending Page	123
File Size	631386
Page Count	6
File Format	PDF
ISBN	9781424444656
DOI	10.1109/SOCC.2009.5335663
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-05
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design methodology Design optimization Integrated circuit technology Space technology Electronic design automation and methodology Space exploration System-level design Integrated circuit packaging Cost function Video coding High-Level Synthesis 3D-Stacked Integrated Circuits Virtual Prototyping
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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