NDLI: Is Your Low Power Design Switched On?

Content Provider	IEEE Xplore Digital Library
Author	Croft, M. Bailey, S.
Copyright Year	2007
Description	Author affiliation: Mentor Graphics, Wilsonville (Croft, M.; Bailey, S.)
Abstract	Power is the key driver in most electronic systems design. Managing system power to increase battery life and reduce electricity consumption and heat generation are key considerations in developing many types of systems from mobile handsets, portable navigation systems and compute servers. New design techniques including clock gating, power gating, multi-voltage and dynamic voltage and frequency scaling have been employed to reduce both dynamic and static energy consumption. The design of low power electronic systems creates new design and verification challenges. Today's systems-on-chip are composed of large IP blocks approaching and exceeding 1 million gates. How can the system low power design intent be applied without requiring modification to and time consuming re-verification of the IP's golden RTL code? How can the functional impacts of power gating, retention and isolation be verified early in the design process when it is cheaper and easier to fix problems? Can implementation-dependent low power design functionality such as accurate retention save and restore protocols be verified prior to synthesis? In this presentation, we will discuss Accellcra's Unified Power Format standard for low power design intent and using UPF for verification.
Starting Page	1
Ending Page	4
File Size	2993932
Page Count	4
File Format	PDF
ISBN	9781424413676
DOI	10.1109/ISSOC.2007.4427451
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-20
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Driver circuits Battery management systems Energy management Power system management Power generation Mobile handsets Navigation Portable computers Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in