NDLI: High Throughput Multi-port MT19937 Uniform Random Number Generator

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High Throughput Multi-port MT19937 Uniform Random Number Generator

Content Provider	IEEE Xplore Digital Library
Author	Sriram, V. Kearney, D.
Copyright Year	2007
Description	Author affiliation: Univ. of South Australia, Adelaide (Sriram, V.; Kearney, D.)
Abstract	There have been many previous attempts to accelerate MT19937 using FPGAs but we believe that we can substantially improve the previous implementations to develop a higher throughput and more area time efficient design. In this paper we first present a single port design and then present an enhanced 624 port hardware implementations of the MT19937 algorithm that has a throughput of 119.6 x $10^{9}$ 32 bit random numbers per second, which is more than 17 times that of the previously best published uniform random number generator. Furthermore it has the lowest area time metric of all the currently published FPGA based pseudo uniform random number generators.
Starting Page	157
Ending Page	158
File Size	87991
Page Count	2
File Format	PDF
ISBN	0769530494
DOI	10.1109/PDCAT.2007.47
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-03
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Random number generation Field programmable gate arrays Logic Acceleration Hardware Feedback Shift registers Distributed computing Algorithm design and analysis
Content Type	Text
Resource Type	Article

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