NDLI: A FPGA Implementation of Variable Kernel Convolution

Content Provider	IEEE Xplore Digital Library
Author	Sriram, V. Kearney, D.
Copyright Year	2007
Description	Author affiliation: Univ. of South Australia, Adelaide (Sriram, V.; Kearney, D.)
Abstract	Convolution is a basic signal and image processing application. In image processing, kernel coefficients of convolution commonly remain constant across the entire image. A less common situation is where the kernel coefficients change in value for each pixel in the image. We call this variable kernel convolution. In this paper we present what we believe are the first three FPGA implementations of variable kernel convolution. The first uses sequential streaming, the second uses pipelining and the third solution uses what we call convolve and gather and its hardware implementation has the highest area time rating (6.7 x better than streaming and 3.4x better than the pipelining solution). Both pipelining and convolve and gather have the same throughput (which is 25 x that of streaming), but convolve and gather has 71% smaller area footprint than the pipeline.
Starting Page	105
Ending Page	110
File Size	200702
Page Count	6
File Format	PDF
ISBN	0769530494
DOI	10.1109/PDCAT.2007.45
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-12-03
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Kernel Convolution Pipeline processing Image processing Signal processing Pixel Streaming media Hardware Throughput
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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