NDLI: Time and Frequency Domain Modeling, Simulation, and Measurement of a Non-Standard Cabled PCI Express® Channel

Content Provider	IEEE Xplore Digital Library
Author	Germann, P. Doyle, M. Ericson, R. Patel, A.
Copyright Year	2008
Description	Author affiliation: IBM Corp., Rochester, MN (Germann, P.; Doyle, M.; Ericson, R.; Patel, A.)
Abstract	$PCI-Express^{reg1}$ specifications have recently been updated to account for transmission across a cabled interface. These specifications are intended to be used with a "standard" cable, and budgeted according to the channel losses and jitter. This paper describes the design and verification of four x8 $PCIe^{reg}$ channels which are neither a standard motherboard/plug-in interface, nor a standard cable interface. The channel consists of a commercially available bridge chip and an IBM ASIC driven through two printed circuit boards, two $GigArray^{reg}$ High-Speed Mezzanine connectors, and a flex cable. Total channel length is roughly 25 inches (~64 cm), with nearly 15 inches in the flex cable. Standard-loss and low-loss dielectric laminates were considered for the flex cable, significant effort was spent carefully designing the flex element. A standard frequency-domain simulator was used to estimate the channel loss based on known transmission constructs in the PCBs and flex cable. Budgets were developed to the PCIe specifications and enforced with PCB and flex cable design constraints from analysis and spec requirements. Prototypes were fabricated in both standard-loss and low-loss materials, and measurements were made on both sets of hardware. A software compliance package (installed on a digital sampling oscilloscope) was used to judge the performance of the channel during system operation. Time-domain $HSPICE^{reg}$ simulation was used to achieve model-to-hardware correlation, and in-situ VNA measurements were used to correlate channel loss budgets in the frequency domain. Based on measurements and analysis, the interface margin on the subsequent production pass of the hardware designs was significantly improved.
Starting Page	1
Ending Page	4
File Size	4081295
Page Count	4
File Format	PDF
ISBN	9781424423170
DOI	10.1109/SPI.2008.4558395
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-12
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency domain analysis Frequency measurement Time measurement Hardware Jitter Bridge circuits Application specific integrated circuits Flexible printed circuits Connectors Dielectrics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Extending Cabled PCI Express to Connect Devices with Independent PCI Domains

On-Chip Circuit for Measuring Data Jitter in the Time or Frequency Domain

Modeling and simulation of signaling channel loss on printed circuit board

The importance of using time domain to analyze the effect of decoupling capacitor performance on printed circuit boards

System simulation of printed circuit boards including packages and connectors

A frequency domain fast wavelet collocation method for high-speed circuit simulation

The effect of decoupling capacitor distance on printed circuit boards using both frequency and time domain analysis

Time domain simulation of the effect of decoupling capacitor location on printed circuit boards

Nonorthogonal PEEC formulation for time and frequency domain modeling

Time and Frequency Domain Modeling, Simulation, and Measurement of a Non-Standard Cabled PCI Express® Channel

Similar Documents

Extending Cabled PCI Express to Connect Devices with Independent PCI Domains

On-Chip Circuit for Measuring Data Jitter in the Time or Frequency Domain

Modeling and simulation of signaling channel loss on printed circuit board

The importance of using time domain to analyze the effect of decoupling capacitor performance on printed circuit boards

System simulation of printed circuit boards including packages and connectors

A frequency domain fast wavelet collocation method for high-speed circuit simulation

The effect of decoupling capacitor distance on printed circuit boards using both frequency and time domain analysis

Time domain simulation of the effect of decoupling capacitor location on printed circuit boards

Nonorthogonal PEEC formulation for time and frequency domain modeling

Time and Frequency Domain Modeling, Simulation, and Measurement of a Non-Standard Cabled PCI Express® Channel