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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yue-Fang Kuo Ro-Min Weng Chuan-Yu Liu |
| Copyright Year | 2005 |
| Description | Author affiliation: Department of Electrical Engineering, National Dong Hwa University, Taiwan, R. O. C. (Yue-Fang Kuo) |
| Abstract | A fast locking phase-locked loops (PLL) with a phase error detector (PED) circuit is presented. The PED circuit is composed of a dual-slop phase frequency detector and a charge-pump characteristic. The proposed architecture can efficiently reduce both the power dissipation and the acquisition time of the PLL while the loop stability remains unchanged. The proposed PLL is designed in a standard CMOS 0.35μm technology through a 3.3V power supply. The simulation results show that the settling time of the proposed PLL is below 150ns. There is over 50% reduction of the locked time in comparison with the conventional PLLs. The power consumption is 18.5mW at 2.4GHz. |
| Starting Page | 423 |
| Ending Page | 426 |
| File Size | 1312080 |
| Page Count | 4 |
| File Format | |
| ISBN | 0780393392 |
| DOI | 10.1109/EDSSC.2005.1635297 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops Phase detection Phase frequency detector Bandwidth Circuits Phase noise Charge pumps Voltage-controlled oscillators Filters Power dissipation charge pump Phase-Locked Loop phase error detector lock detector dual-slop phase frequency detector |
| Content Type | Text |
| Resource Type | Article |
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