NDLI: Switched capacitor architecture for prime length discrete Hartley transform

Content Provider	IEEE Xplore Digital Library
Author	Mal, A.K. Dhar, A.S.
Copyright Year	2003
Description	Author affiliation: Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India (Mal, A.K.; Dhar, A.S.)
Abstract	This paper describes an analog VLSI architecture, capable of computing discrete Hartley transform (DHT), and its inverse, for any prime N and its multiple of two and four, using standard analog blocks. The scheme operates from the general expression of DHT where the Input samples are multiplied by all the DHT coefficients, simultaneously using an array of capacitors. These multiplied values are then switched simultaneously with the help of cross point switch, to different integrators for performing necessary addition/subtraction. Here switched capacitor integrators are used to compute the transform, with capacitor ratios controlling the kernel coefficients. Proposed scheme shares maximum hardware when kernel coefficients pattern become regular. It is shown that for multiples of two and four, the same module used for primes can be reused and thus gives a modular architecture. It is suitable for real time applications with reasonable accuracy.
Sponsorship	IEEE Electron Devices Soc. IEEE Solid-State Circuits Soc. IEEE Hong Kong Section Hong Kong Univ. of Sci. and Technol. K.C. Wong Found. Fong's Family Found. Mr. Lim Por Yen
Starting Page	505
Ending Page	508
File Size	302817
Page Count	4
File Format	PDF
ISBN	0780377494
DOI	10.1109/EDSSC.2003.1283582
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitors Discrete transforms Kernel Signal processing algorithms Computer architecture Switches Algorithm design and analysis Digital signal processing Image coding Very large scale integration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Analog sampled data architecture for discrete Hartley transform for prime N

Analog VLSI architecture for discrete cosine transform using dynamic switched capacitors

An efficient design for one-dimensional discrete Hartley transform using parallel additions

A systolic circuit for fast Hartley transform

Analog sampled data architecture for discrete Hartley transform

New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform

Systolic circuits for fast transform algorithms

A High Rate VLSI circuit For the radix-2 Fast Hartley Transform

Digital controlled analog architecture for DCT and DST using capacitor switching

Switched capacitor architecture for prime length discrete Hartley transform

Similar Documents

Analog sampled data architecture for discrete Hartley transform for prime N

Analog VLSI architecture for discrete cosine transform using dynamic switched capacitors

An efficient design for one-dimensional discrete Hartley transform using parallel additions

A systolic circuit for fast Hartley transform

Analog sampled data architecture for discrete Hartley transform

New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform

Systolic circuits for fast transform algorithms

A High Rate VLSI circuit For the radix-2 Fast Hartley Transform

Digital controlled analog architecture for DCT and DST using capacitor switching

Switched capacitor architecture for prime length discrete Hartley transform