NDLI: Hierarchical redundancy for orthogonal arrays

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Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

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Hierarchical redundancy for orthogonal arrays

Content Provider	IEEE Xplore Digital Library
Author	Tsuda, N.
Copyright Year	1992
Description	Author affiliation: NTT Commun. & Inf. Processing Lab., Tokyo, Japan (Tsuda, N.)
Abstract	Hierarchical redundancy using defect-tolerant replacement circuits is proposed for increasing the yield of large-area LSIs (WSIs) with mesh-connected array structures. The defect-tolerant replacement circuits can be constructed by using direct-connection paths and distributed switches in basic k-out-of-n redundancy schemes. When the proposed redundancy configurations are applied to two-dimensional orthogonal-array WSIs (wafer-scale-integrated circuits), they reduce the number of switches not covered by any spare replacements. An estimate of defect tolerance indicates that the proposed redundancy configurations can increase the integration scale under 1-micron CMOS design about 256 times over that of general nonredundant LSIs.
Starting Page	220
Ending Page	229
File Size	333632
Page Count	10
File Format	PDF
ISBN	0818624825
DOI	10.1109/ICWSI.1992.171814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-01-22
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Redundancy Switches Switching circuits Integrated circuit interconnections Information processing Laboratories Communication switching Wafer scale integration Parallel processing CMOS technology
Content Type	Text
Resource Type	Article

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