NDLI: A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization

Content Provider	IEEE Xplore Digital Library
Author	Jeschke, H. Wehberg, T.W. Volkers, K.
Copyright Year	1991
Description	Author affiliation: Lab. fuer Informationstechnol., Hannover Univ., Germany (Jeschke, H.; Wehberg, T.W.; Volkers, K.)
Abstract	A novel MIMD (multiple instruction multiple data) based multiprocessor architecture consisting of multiple processing elements (PE) has been developed for real-time image processing. Each PE contains an arithmetic processing unit adapted to convolution-like low-level operations and a high-level and control processor. A high-speed random access to local image data is provided by two local input memories and an I/O and feedback unit. This architecture has a high regularity at the task level which is suitable for a WSI (wafer scale integration) implementation. The main parts of a PE have been realized as VLSI test chips providing a computational rate of up to 400 MOPS for one PE.
Starting Page	40
Ending Page	46
File Size	390263
Page Count	7
File Format	PDF
ISBN	0818691263
DOI	10.1109/ICWSI.1991.151694
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-01-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image processing Multiprocessing systems Very large scale integration System testing Real time systems Redundancy Discrete cosine transforms Digital signal processing chips Laboratories Arithmetic
Content Type	Text
Resource Type	Article

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