NDLI: A defect and fault tolerant design of WSI static RAM modules

Content Provider	IEEE Xplore Digital Library
Author	Tsuda, N.
Copyright Year	1990
Description	Author affiliation: NTT Commun. & Inf. Process. Labs., Kanagawa, Japan (Tsuda, N.)
Abstract	Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration.
Starting Page	213
Ending Page	219
File Size	354720
Page Count	7
File Format	PDF
ISBN	0818690135
DOI	10.1109/ICWSI.1990.63903
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-01-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Redundancy Error correction Information processing Laboratories Semiconductor device modeling Circuit faults CMOS technology Random access memory Logic circuits
Content Type	Text
Resource Type	Article

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