NDLI: Optimal switching networks for WSI architectures with fault tolerant path routing

Please wait, while we are loading the content...

Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI)

Wafer-scale embedded-MPC modules for cost-effective image processing systems

Complex-argument universal nonlinear cell for rapid prototyping wafer architecture

The WASP-3 monolithic-WSI massively parallel processor

Test vehicle for a wafer-scale field programmable gate array

The digital micromirror device for projection display

A life cycle model for the WSI associative string processor (WASP)

Three dimensional stacking with diamond sheet heat extraction for subnanosecond machine design

Teaching the efficient use of hybrid-WSI technology

A RAM-based neural network architecture for wafer scale integration

A module-sliced high yield WSI memory system

A neural algorithm for reconstructing mesh-connected processor arrays using single-track switches

Time redundancy for error detecting neural networks

Silicon hybrid wafer scale integration (SHWSI)-a discrete integrated circuit (IC) interconnect scheme

CCD wafer scale integration

A substrate area estimation technique for Multi-Chip Modules

Defect-tolerant hypercube architectures using hierarchical redundancy

Optimal switching networks for WSI architectures with fault tolerant path routing

A hierarchical redundant cube-connected cycle for WSI yield enhancement

Stream oriented fault tolerant array

A wafer-scale ATM switching system based on the Manhattan-street network

A comparison of VLSI, MCM and WSI technologies

An experimental fault-tolerant active substrate MPC MCM using standard gate array technology

Yield improvement of a large area magnetic field sensor array design using redundancy schemes

Large integrated crossbar switch

Defect-tolerant processor arrays

A cache coherency protocol for multiprocessor chip

The influence of process parameter variations on the signal distribution behaviour of wafer scale integration devices

High-speed interconnections using true single-phase clocking

Innovative design of CMOS fault tolerant structures

An evaluation of defect and fault tolerant signal routing strategies for WASP devices

A post-processing algorithm for short-circuit defect sensitivity reduction in VLSI layouts

Reconfiguration and routing in defective WSI processor arrays

Yield analysis of fault-tolerant multichip module systems for massively parallel computing

Yield and performance issues in fault-tolerant WSI array architectures

The impact of floorplanning on the yield of fault-tolerant ICs

Towards WSI testable devices: an improved scan insertion technique

An easily-testable cube-connected cycles structure

Algorithms for arithmetic operation in a systolic array of single-bit processor (SASP)

Test strategies for multi-chip modules based on economics considerations

21st century gigascale integration (GSI)

Proceedings of 1994 International Conference on Wafer Scale Integration (ICWSI)

1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration

[1992] Proceedings International Conference on Wafer Scale Integration

1991 Proceedings, International Conference on Wafer Scale Integration

1990 Proceedings. International Conference on Wafer Scale Integration

[1989] Proceedings International Conference on Wafer Scale Integration

Optimal switching networks for WSI architectures with fault tolerant path routing

Content Provider	IEEE Xplore Digital Library
Author	Liu, T. Lombardi, F.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA (Liu, T.; Lombardi, F.)
Abstract	This paper presents an approach for designing fault-tolerant routers for signal distribution by redundant path routing in wafer scale integration (WSI) architectures. The conditions by which a router can be designed using spare lines (tracks) such that the probability of successfully routing all input lines in the prescribed order and in the presence of faults in switches can be optimized (optimality), are proved using a probabilistic analysis. An algorithm which determines the placement of the switches in the router to satisfy the optimality conditions is presented.
Starting Page	153
Ending Page	162
File Size	473342
Page Count	10
File Format	PDF
ISBN	0780324676
DOI	10.1109/ICWSI.1995.515449
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-01-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Routing Computer architecture Switches Application specific processors Wafer scale integration Computer aided manufacturing Topology Computer science Signal design
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in