NDLI: Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs

Content Provider	IEEE Xplore Digital Library
Author	Basu, S. Vemuri, R.
Copyright Year	2007
Description	Author affiliation: Dept. of ECE, Cincinnati Univ., OH (Basu, S.; Vemuri, R.)
Abstract	Negative bias temperature instability (NBTI) has become a growing concern in nanometer technologies. It may reduce the lifetime of reliable operation of PMOS transistors in the design. Process variation has started impacting the nanometer ICs by reducing the parametric yield. Process variation together with NBTI can further reduce the reliable lifetime of ICs. Conventional ASIC design methodology uses pre-characterized standard cells to optimize the design as per specifications. The standard cells occupy nearly 75% of the chip real estate in a sea-of-gate design. Therefore process variation and NBTI tolerant robust standard cells may help in reducing the margin of performance variation thereby increasing the lifetime of reliable operation. The use of robust cells may further help in reducing the design time overhead. In this work, the authors model the combined effect of process variation and NBTI on intrinsic gate delay using a reduced dimension modeling technique. The authors use the models to optimize the standard cells in the presence of NBTI and process variations with a target lifetime of 10 years. Experimental results show that the use of optimized robust standard cells can considerably improve the tolerance of circuit in the self-timed sections of critical timing paths.
Sponsorship	IEEE Comput. Soc. Tech. Comm. VLSI
Starting Page	291
Ending Page	298
File Size	384712
Page Count	8
File Format	PDF
ISBN	0769528961
DOI	10.1109/ISVLSI.2007.85
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-09
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Niobium compounds Titanium compounds Robustness Negative bias temperature instability MOSFETs Application specific integrated circuits Design methodology Design optimization Delay effects Timing
Content Type	Text
Resource Type	Article

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NBTI-Aware Synthesis of Digital Circuits

Multi-corner, energy-delay optimized, NBTI-aware flip-flop design

Calculation of stress probability for NBTI-aware timing analysis

NBTI in dual gate oxide PMOSFETs

Aging-resilient design of pipelined architectures using novel detection and correction circuits

Impact of negative bias temperature instability on product parametric drift

Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI

Modeling and minimization of PMOS NBTI effect for robust nanometer design

Scheduled voltage scaling for increasing lifetime in the presence of NBTI

Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs

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