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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hao Li Wai-Kei Mak Katkoori, S. |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Comput. Sci. & Eng., South Florida Univ., Tampa, FL, USA (Hao Li; Wai-Kei Mak; Katkoori, S.) |
| Abstract | We propose a net-based force-directed performance-driven placement algorithm for hierarchical FPGAs. The input netlist is first transformed into a net dependency graph. Then we partition this graph into clusters and a net-cluster level floorplan is derived by simulated annealing. Force-directed net placement is performed to generate a coarse net-level placement. Next, a force-directed logic cell placement is computed iteratively. Finally, we assign I/O pins using a modified Munkres' algorithm. The main contribution of our work is that we apply force-directed method in hierarchical FPGAs to improve delay as compared to Xilinx tools. We improve the post-layout delay and average connection delay by an average of 10.2% and 19.3% respectively over a set of MCNC combinational benchmark. We also improve the maximum clock frequency by an average of 20.7% over a set of MCNC sequential circuits. |
| Sponsorship | IEEE Comput. Soc. Center for Advanced Comput. Studies Univ. of Louisiana at Lafayette |
| Starting Page | 193 |
| Ending Page | 198 |
| File Size | 655365 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769520979 |
| DOI | 10.1109/ISVLSI.2004.1339529 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-02-19 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Clustering algorithms Partitioning algorithms Delay Computational modeling Simulated annealing Logic Pins Iterative algorithms Clocks |
| Content Type | Text |
| Resource Type | Article |
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