NDLI: Usage of application-specific switching activity for energy minimization of arithmetic units

Content Provider	IEEE Xplore Digital Library
Author	Shu-Shin Chin Sangjin Hong Suhwan Kim
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Stony Brook Univ., NY, USA (Shu-Shin Chin; Sangjin Hong)
Abstract	This paper presents a delay constraint power minimization technique for logic incorporating dual supply voltages. The power is reduced by selecting supply voltage according to switching activity of the subunits. The technique employs energy and delay models of arithmetic units with array structure. The supply voltage is selected to reduce power consumption while maintaining propagation delay constraint. The model characterization is done with Verilog simulation where subunits are designed with Cadence and HSPICE using 0.35/spl mu/m CMOS process. We applied the technique on multiplier of general purpose DSP processors and CORDIC. The results obtained from the proposed method are discussed.
Sponsorship	IEEE Comput. Soc. Center for Advanced Comput. Studies Univ. of Louisiana at Lafayette
Starting Page	158
Ending Page	163
File Size	1515787
Page Count	6
File Format	PDF
ISBN	0769520979
DOI	10.1109/ISVLSI.2004.1339524
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Arithmetic Voltage Semiconductor device modeling Minimization Logic Energy consumption Propagation delay Hardware design languages CMOS process Digital signal processing
Content Type	Text
Resource Type	Article

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