NDLI: Low-power driven scheduling and binding

Content Provider	IEEE Xplore Digital Library
Author	Crenshaw, J. Sarrafzadeh, M.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA (Crenshaw, J.)
Abstract	We investigate the problem of exploiting signal correlation between operations to find a schedule and binding which minimizes switching. We propose several heuristics to solve the problem. Experimentally, we give an algorithm for scheduling communications on a bus, which reduces bus switching up to 60%, without increasing the number of cycles required for the schedule. Low-power scheduling efforts in the literature have focused on decreasing the number of cycles in the schedule so that the voltage required to run the resulting circuit can be lowered. However, the number of voltages supplied to a chip is likely to be limited, so among the processes to be implemented, typically only a few will determine the minimum voltages, and the rest will have slack in their schedules. Therefore it is interesting to inquire about the impact of scheduling which does not reduce the number of time steps in order to decrease switching. In this paper, we show that power-aware scheduling can lead to significant decreases in switching, often without an increase in the number of time steps required. The technique is general, and can be used to schedule operations on any kind of resources.
Starting Page	406
Ending Page	413
File Size	62591
Page Count	8
File Format	PDF
ISBN	0818684097
ISSN	10661395
DOI	10.1109/GLSV.1998.665335
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-02-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Communication switching Scheduling algorithm Circuits
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A low power register scheduling and allocation algorithm for multiple voltage

Zero switching low output voltage power factor correction circuits

Operation binding and scheduling for low power using constraint logic programming

Low Power Binding for Switching Activity Reduction Based on Table Decomposition Method

An algorithm for power estimation in switched-capacitor circuits

Switched inverter - A new technique for sample data low-voltage and low-power applications

Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment

Clock boosters for 1.2-V SC circuits

A single switch high power factor battery charger

Low-power driven scheduling and binding

Similar Documents

A low power register scheduling and allocation algorithm for multiple voltage

Zero switching low output voltage power factor correction circuits

Operation binding and scheduling for low power using constraint logic programming

Low Power Binding for Switching Activity Reduction Based on Table Decomposition Method

An algorithm for power estimation in switched-capacitor circuits

Switched inverter - A new technique for sample data low-voltage and low-power applications

Dynamic and Leakage Power Minimization with Loop Voltage Scheduling and Assignment

Clock boosters for 1.2-V SC circuits

A single switch high power factor battery charger

Low-power driven scheduling and binding