NDLI: A low power register scheduling and allocation algorithm for multiple voltage

Content Provider	IEEE Xplore Digital Library
Author	Choi, J.-Y. Lin, C.-H. Kim, H.-S.
Copyright Year	2001
Description	Author affiliation: Dept. of Electron. Eng., Chongju Univ., China (Choi, J.-Y.)
Abstract	The low power register scheduling and allocation algorithm is concerned with minimum switching activity and low power multiple voltages. The proposed algorithm executes low power scheduling to reduce switching activity using a shut down technique by the creation of a data flow graph (DFG) from the VHDL description. Also, the low power register allocation algorithm determines the minimum register after the life time analysis of all variables. It minimizes the switching activity using a graph coloring technique for low power consumption. Finally, the total power is reduced by using the low power multiple voltage. The proposed algorithm proves the effect through various filter benchmarks to adopt a low power register scheduling and allocation algorithm considering resource constraint at multiple voltage.
Sponsorship	IEEE Region 10
Starting Page	627
Ending Page	630
File Size	354430
Page Count	4
File Format	PDF
ISBN	0780371011
DOI	10.1109/TENCON.2001.949669
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-08-19
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Scheduling algorithm Registers Power dissipation Processor scheduling Energy consumption Switching circuits Low voltage Filters Resource management Very large scale integration
Content Type	Text
Resource Type	Article

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