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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gent, K. Hsiao, M.S. |
| Copyright Year | 2015 |
| Description | Author affiliation: Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA (Gent, K.; Hsiao, M.S.) |
| Abstract | Functional test generation and design validation frequently use stochastic methods for vector generation. However, for circuits with narrow paths or random-resistant corner cases, purely random techniques can fail to produce adequate results. Deterministic techniques can aid this process; however, they add significant computational complexity. This paper presents a Register Transfer Level (RTL) abstraction technique to derive relationships between inputs and path activations. The abstractions are built off of various program slices. Using such a variety of abstracted RTL models, we attempt to find patterns in the reduced state and input with their resulting branch activations. These relationships are then applied to guide stimuli generation in the concrete model. Experimental results show that this method allows for fast convergence on hard-to-reach states and achieves a performance increase of up to 9× together with a reduction of test lengths compared to previous hybrid search techniques. |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 978544 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781479975976 |
| DOI | 10.1109/VTS.2015.7116286 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-04-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Benchmark testing IEEE Computer Society Engines Optimization Pipelines Instruments Databases |
| Content Type | Text |
| Resource Type | Article |
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