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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dworak, J. Crouch, A. |
| Copyright Year | 2015 |
| Description | Author affiliation: ASSET InterTech, Inc., Richardson, TX, USA (Crouch, A.) || Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA (Dworak, J.) |
| Abstract | Today's chips often contain a wealth of embedded instruments, including sensors, hardware monitors, built-in self-test (BIST) engines, etc. They may process sensitive data that requires encryption or obfuscation and may contain encryption keys and ChipIDs. Unfortunately, unauthorized access to internal registers or instruments through test and debug circuitry can turn design for testability (DFT) logic into a backdoor for data theft, reverse engineering, counterfeiting, and denial-of-service attacks. A compromised chip also poses a security threat to any board or system that includes that chip, and boards have their own security issues. We will provide an overview of some chip and board security concerns as they relate to DFT hardware and will briefly review several ways in which the new IEEE 1687 standard can be made more secure. We will then discuss the need for an IEEE Security Standard that can provide solutions and metrics for providing appropriate security matched to the needs of a real world environment. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 635550 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479975976 |
| DOI | 10.1109/VTS.2015.7116256 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-04-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Instruments Registers Encryption Ports (Computers) Standards Microprogramming LSIB IEEE Standard DFT P1687 JTAG IJTAG security scan BIST lock trap |
| Content Type | Text |
| Resource Type | Article |
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