NDLI: Pattern generation and estimation for power supply noise analysis

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Pattern generation and estimation for power supply noise analysis

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Pattern generation and estimation for power supply noise analysis

Content Provider	IEEE Xplore Digital Library
Author	Nourani, M. Tehranipoor, M. Ahmed, N.
Copyright Year	2005
Description	Author affiliation: Dept. of EE, Univ. of Texas at Dallas, TX, USA (Nourani, M.)
Abstract	This paper presents an automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 /spl rarr/ 1 and 1 /spl rarr/ 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns was verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum power supply noise.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC)
Starting Page	439
Ending Page	444
File Size	157793
Page Count	6
File Format	PDF
ISBN	0769523145
ISSN	10930167
DOI	10.1109/VTS.2005.65
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power generation Power supplies Noise generators Pattern analysis RLC circuits Circuit noise Switching circuits Voltage SPICE Libraries
Content Type	Text
Resource Type	Article

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