NDLI: 2C: IP Session - DFT for SoCs in Wireless Applications [Breaker page]

Content Provider	IEEE Xplore Digital Library
Copyright Year	2005
Abstract	The advances of deep sub-micron process manufacturing technologies have enabled System-on-Chip designs. On the other hand, they also greatly complicate testing for SoC devices and require advanced test methods such as scan-based at-speed testing. The embedded core design style is widely adopted for SoC designs because the reuse of the previously designed Intellectual Property (IP) cores lowers design costs and shortens time-to-market. However, since such SoC devices incorporate various design technologies (such as microprocessor, static/dynamic/flash/cache memory, high-speed logic/IO and even analog circuits), the complexity of SoC testing further increases and hence sophisticated design-for-testability (DFT) techniques are required. Built-In Self-Test (BIST) is a one of the popular DFT approaches because it not only applies test at-speed, but also reduces test costs. In addition, BIST circuitry of SoC devices can be made accessible via boundary scan architecture (a.k.a JTAG) to facilitate board and system level test. The deployment of 3G wireless systems has significantly elevated the complexity of wireless SoC designs for higher performance and capacity as well as the capability of handling multimedia - such as voice, date, graphics, music and video. Therefore, there are a lot of challenges posed in design and test for wireless SoCs. In this Innovative Practice session, speakers from Bell Labs Lucent Technologies, Qualcomm Inc, and Intel Corp will present the leading edge DFT techniques for their wireless SoC chips used in 3G wireless base stations and handsets.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council (TTTC)
Starting Page	97
Ending Page	97
File Size	28753
Page Count	1
File Format	PDF
ISBN	0769523145
ISSN	10930167
DOI	10.1109/VTS.2005.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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