NDLI: Instruction-driven wake-up mechanisms for Snoopy TAP controller

Content Provider	IEEE Xplore Digital Library
Author	Bhattacharya, D.
Copyright Year	1999
Description	Author affiliation: Converter Product Dev. Center, Texas Instrum. Inc., Dallas, TX, USA (Bhattacharya, D.)
Abstract	The issue of handling multiple embedded 1149.1-compliant TAP controllers (as part of embedded cores) in a 1149.1-compliant IC, has received significant attention, in recent times. The Hierarchical TAP (HTAP) architecture, previously developed by this author, provides a systematic solution to this problem, by allowing multiple embedded TAPs to share one set of 1149.1-specified test pins on the IC. The HTAP architecture requires an augmented version of the 1149.1-specified TAP-designated the Snoopy TAP (SNTAP)-in the top-level of the design hierarchy, that handles 1149.1-specified TAP functions for the non-TAP'ed parts of the IC, and performs arbitration of the shared IC pins between multiple embedded TAPs. Previously, a mechanism was developed to wake up the SNTAP using a simple string of constant values (0 or 1) on the TMS input. Two new mechanisms to wake up SNTAP by means of an instruction scanned in, are described in this report. Both mechanisms allow embedded 1149.1-compliant TAP's to be used in a hierarchical design, as is, without any hardware modification. Moreover, both mechanisms enable reuse of the test program from the embedded TAP'ed cores, without any modification. The instructions to wake up the SNTAP-to switch access to different TAP-ed cores-can be simply inserted in-between the test programs for the embedded cores.
Starting Page	467
Ending Page	472
File Size	267553
Page Count	6
File Format	PDF
ISBN	076950146X
ISSN	10930167
DOI	10.1109/VTEST.1999.766705
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-04-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pins Integrated circuit testing Switches System testing Product development Instruments Traffic control Tin Joining processes Performance evaluation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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